A known PLL configuration includes a voltage controlled oscillator (VCO), a phase detector, a charge pump circuit and a loop filter. U.S. Pat. No. 5,675,291 granted to D. Sudjian on Oct. 7, 1997 discloses a PLL for use in a frequency synthesizer.
U.S. Pat. No. 5,334,951 granted to J. G. Hogeboom on Aug. 2, 1994 discloses a PLL. The prior art charge pump circuit shown in FIG. 2 of the patent is based on a current mirror circuit which includes series-connected field effect transistors (FETs) as switching devices. A VCO signal and an input signal are fed to the phase detector which detects the phase difference between both signals. The phase detector generates two pulse trains responsive to the phase difference. The pulse trains cause the switching FETs to turn-on and -off. In response to one of the pulse trains, the current mirror circuit sources current to the filter via the on-switching FET and, in response to the other pulse train, the current mirror circuit sinks current from the filter via the on-switching FET. As a result, the filter is charged or discharged and the voltage in the filter is fed to the VCO to variably control the frequency of the VCO signal. In some applications of PLLs (e.g., a frequency synthesizer) including the charge pump circuit, the VCO output frequencies are controllably varied and different frequencies require different charge pump circuit output voltages. The source and sink currents are required to be matched to each other at any voltage of the charge pump circuit output. Although the charge pump circuit is designed to have high output impedances to minimize the mismatch, it is difficult to have infinite output impedances and the mismatch is imminent. Any mismatch between the source and sink currents causes undesirable sidebands at the output of the PLL. In a case of the FETs being CMOS (complementary metal oxide semiconductor) devices, the output impedance of the current sourcing FETs becomes very low to provide low output voltage, or voltages near the positive rail.